Distortion system for introducing distortion into a pulse train



Dec. 2, 1969 J, WALLACE, JR 3,482,117

- DISTORTION SYSTEM FOR INTRODUCING DISTORTION INT0 A PULSE TRAIN Filed Match 31, 1966 4 Sheets'Sheet 1 INVENTOR ugHrsEY WALL/EJK Dec. 2, 1969 J. L. WALLACE, JR

DISTORTION SYSTEM FOR INTRODUCING DISTORTION INTO A PULSE TRAIN 4 Sheets-Sheet Filed March 31, 1966 .l C C B E E 6 a m m m s D D M .w M s m FTF TF, FTFTF TF TF TF TF TF TFT q H m 4 d d m l 2 5 P O 0 0 0 0 0 u l y y y y y y l P P P 0 P. 1 l m m w y w m P IIPIII .lllllSlll 5 IS|I| 5 5 -io m T 'lill llllllllllllllllllll 5 5 5 5 5 5 5 5 i |511 illl i 1 I 4 4 4 4 4 4 l 4 llwll 1 I 3 3 3 3 3 3 l 3 3 l 2 2 2 2 2 2 2 Z Il I l l l l |||||J l- Il- ..1 T T T m m J M M M il T A A T T m l m s y w s 5 w m m S S Y TFT FT FT FrFT FT F7 FTFT FT FT FTF A 5 I H I C C B B E E 2 M 5 W C S D D M 5 M s INVENTOR J. L/GHTSEY WAL/ AL`E,JR.

BY I ATTORNEY Dec. 2. 1969 .1. L. WALLACE, JR 3,482,317

DSTORTION SYSTEM FOR INTRODUCING DISTORTION INTO A PULSE TRAIN Filed March 3l. 1966 4 Sheets-Sheet 5 Dec. 2. 1969 J, WALLACE, JR 3,482,117

DISTORTION SYSTEM FOR INTRODUCING DISTORTION INTO A PULSE TRAIN Filed Max-ch 31, 1966 4 Sheets-Sheet 4 D/S TUR TED OUTPUT S/G/VA L INVENTOR @fig- 6 ATTORNEY J. L/GHTSEY u/ALLAce,JR.

United States Patent() 3,482,117 DISTORTION SYSTEM FOR INTRODUCING DISTORTION INTO A PULSE TRAIN Jacob L. Wallace, Jr., Springfield, Va., assigner to The Susquehanna Corporation, a corporation of Delaware Filed Mar. 31, 1966, Ser. No. 539,002 Int. Cl. H03k 3/64 U.S. Cl. 307-265 18 Claims ABSTRACT OF THE DISCLOSURE As an illustration of the subject system, assume that a telegraph code train is being generated and that it is desired to distort these signals so that the output contains marking bias. These generated signals are delayed one-half of a unit pulse length and both the generated signals and the delayed signals are applied to a gate. Selected logical states, e.g. True or False, of these signals form one-half unit pulse periods when marking bias can occur, at which time the gate is enabled. A generated distortion marker, corresponding to the desired percentage distortion, passes through the enabled gate and causes the space-to-mark transition of the output signal to advance. In this manner the output code train contains marking bias of the desired percentage.

This invention relates to code generators and more particularly to distortion systems therefor.

In the actual operation of communication systems, such as telegraph or data systems utilizing the well-known start-stop or the equally well-known synchronous permutation code signals, the individual signal impulses often become distorted. In order to obtain the proper operation of such systems it is necessary to design the communication equipment or apparatus to tolerate this pulse distortion; otherwise, the transmission and recordation of spurious or faulty signals will occur. Distortion of signals manifests itself in a number of ways to either increase or decrease the duration of the pulses. In the present description four types of distortion will be referred to, namely: marking bias, spacing bias, marking end distortion, and spacing end distortion.

By marking bias it is meant that the space-to-mark transition of each marking pulse in a start-stop telegraph signal has been advanced with respect to the normal markto-space transition occurring at the initiation of each start impulse. In a like manner, the term spacing bias designates a condition wherein the space-to-mark transition of each marking pulse is retarded with respect to the initiation of the start impulse. The term marking end distortion refers to a condition Where the normal mark-tospace transition of each marking pulse in a signal is retarded with respect to the initiation of the start impulse. Conversely, the term spacing end distortion indicates a condition wherein the normal mark-to-space transition of each marking pulse in a signal is advanced with respect to the initiation of the start impulse. The mark-tospace transition at the end of the stop pulse is the beginning of the next start pulse, the reference point of all transmissions, and should not be affected.

In properly designed equipment distortion in the amount of 40% and greater, marking or spacing, can be accommodated and not interfere with normal operation. Accordingly, it is necessary that frequent checks be made of the equipment both at the time of initial manufacture and also after installation has been accomplished to ascertain if the equipment can in fact properly function upon receipt of distorted signals. Previously, signal generators of a variety of designs have been proposed for maintaining and evaluating communication systems which Patented Dec. 2, 1'969 generate signals of various xed speeds at which the communication equipment is capable of operation. The signals are generated with precise percentages of the various types of distortion.

l It is an object of the present invention to provide an lmproved distortion system for operating upon a generated code train to distort same by a predetermined amount.

Another object is the provision of an improved distortion system which is capable of distorting a code train by predetermined types and amounts of distortion.

Another object of the present invention is the provision of a novel distortion system which utilizes a generated code train and a delayed code train to determine the type of distortion for the output signals.

A further object of this invention is to provide an improved code generator for producing signals having preselected types and amounts of distortion introduced into the code impulses.

Another object is to provide an improved code generator for generating undistorted signals and then distorting same by a predetermined amount.

Still another object is to provide an improved code generator for generating undistorted signals and then distorting same by a predetermined type and amount.

A still further object is to provide a simplified distortion system which is designed to receive a generated code train, such as a telegraph or data code train, and selectively combine it with a delayed code train to produce the desired type of distortion in the output code train.

With these and other objects in view, the present invention utilizes the concept of establishing one-half unit pulse periods during which only the desired type of distortion can be created. By providing a code train and delaying same by one-half unit pulse, selective logical states of these signals, and their inverse, are utilized to form these one-half unit pulse periods.

As an illustrative example, assume that a telegraph code train is being generated and that it is desired to distort these signals so that the output contains marking bias. These generated signals are delayed one-half of a unit pulse length and both the generated Signals and the delayed signals are applied to a gate. Selected logical states, e.g. True or False, of these signals form one-half unit pulse periods when marking bias can occur, at which time the gate is enabled. A generated distortion marker, corresponding to the desired percentage distortion, passes through the enabled gate and causes the space-to-mark transition of the output signal to advance. In this manner the output code train contains marking bias of the desired percentage.

Other objects and advantages of the present invention will become apparent from the following detailed description, when considered in conjunction with the accompanying drawings, wherein:

FIGURE l is a conventional block-diagram showing of a start-stop telegraph code generator in conjunction with distortion circuitry;

FIGURE 2 is a set of waveforms occurring at selected points in the other figures;

FIGURE 3 shows an embodiment of the distortion circuits portion of FIGURE 1; and

FIGURES 4, 5, and 6 are logical circuit diagrams of embodiments of the distortion logic portion of the distortion circuit of FIGURE 3;

FIGURE 7 is a modification of FIGURES 1 and 3 for generating certain signals used in the embodiment of ,FIGURE 6.

In FIGURE 1 there is shown a system which can be considered conventional in form for generating undistorted start-stop telegraph code signals. These signals are grouped into characters which are applied along with certain other signals to what is termed broadly Distortion Circuits identiiied by numeral 10. These distortion circuits will be described in more detail in conjunction with the remaining gures.

The character generator FIGURE 1 is driven by oscillator 12 which is here chosen to run at the rate of twenty times the unit pulse rate of the output character. In other words, twenty pulse cycles are generated and applied to counter 14 by line 16 during each unit pulse of the output character. The speed of the oscillator 12 is generally made variable so that characters can be generated at various speeds.

Counter 14 is conventional in construction and is here shown as an up-down counter. Counter 14 serves to divide the input pulses from oscillator 12 by ten so that for each ten pulse cycles applied to counter 14, one output spike is passed to the toggle input of Hip-flop 18 by line 20. These spikes are shown in line A of the waveforms of FIGURE 2. The one output of flip-flop 18 is designated 2B and the zero output, 5E. When ilip-flop 1S is set, 2B is True. When ilip-op 18 is clear, 2 3- is True. These signals, therefore, are the inverse of one another and their respective waveforms are shown in FIGURE 2. Distributor 22, which is driven by the 2B signal, is also conventional in construction and has eight output lines 24a-24h. From these lines are obtained the unit pulses for forming a tive-element, start-stop telegraph character comprising a unit start pulse, iive information bits and a two-unit stop pulse.

Lines 24 are connected to a switch Abank 26. Lines 24!) through 24]r terminate at switches 28b through 28], respectively. These switches are usually mounted externally on the equipment so that they may be readily manipulated by the user to select any desired combination of information bits in the generated telegraph signal. The closure of any switch 28 causes a marking pulse to be generated for that bit while leaving the switch open causes a spacing pulse to be generated. Line 24a, corresponding to the start pulse position in the character, terminates in an open condition Within the switch bank 26, because the start pulse is a spacing condition. Lines 24g and 24h, corresponding to the stop pulse positions, continue through the switch bank 26 because the stop pulse is always represented by a marking condition. The output side of switch bank 2'6 is connected to an OR gate 30 at which the pulses are serially combined to form an undistorted code train which is passed by line 31 to the distortion circuits 10. With the switches 28 set as shown and the system of FIGURE 1 in operation, the character shown in the line CH of FIGURE 2 will be continuously generated.

In regard to the detailed operation of the system of FIGURE 1, the up-down counter 14 is initially at zero and nip-flop 18 is set. Counter 14 advances to a count of ten in response to ten input pulses from oscilllator 12. This corresponds to a one-half unit pulse period. A triggering spike is passed to the toggle input of iiip-iiop 18 to change it from the set state to the clear state. The next ten input pulses from oscillator 12 cause the up-down counter 14 to count down from ten to zero at which time another spike toggles ilip-op 18 to the set state. Thus, ipflop 18 is set at the beginning of each unit pulse period, cleared at the half-way point and then again set at the beginning of the next unit pulse period.

Each time flip-flop 18 is set, the 2B signal goes logically True and this transition is used to advance distributor 22. Initially, the first stage of distributor 22 is activated and a True output condition appears at line 24a. Each time that flip-Hop 18 is set, distributor 22 advances one step. The True output condition steps along lines 24 from line 24a through line 24h. After the True output condition has existed on line 24h for one unit pulse period, it steps back to line 24a when the 2B signal advances distributor 22, and the cycle repeats. If a complete path is provided from an output line 24 to the OR gate 30, then the undistorted character CH formed on line 31 registers a True condition. If the path from an output line 24 to the OR gate 30 is incomplete or interrupted, then a False condition appears in the generated character on line 31. For example, line 24a is open and a False condition is applied to the OR gate 30 when the iirst stage of distributor 22 is conducting. Switches 28b and 28C are closed; therefore, True signals are applied to OR gate 30 when the corresponding stages of distributor 22 activates. Switch 28d is open, resulting in a False condition at OR gate 30; switch 28e is closed-True; switch 28f is open- False; and lines 24g and 24h form a complete path to OR gate 30 and provide True conditions when their respective stages activate. These signals are serially combined into a train to form the representative character CH shown in FIGURE 2. This generated, undistorted character is fed by line 31 to distortion circuits 10.

The distortion circuits are also supplied with additional signals. These are the 2B and 2E signals previously described, and a start-inhibit signal which is identitled by SI in the waveforms of FIGURE 2. The startinhibit line is connected to line 24a leading out of distributor 22. This start-inhibit signal is True when the first stage of distributor 22 is conducting during the generation of the start pulse of the character. At all other times Slis False.

Counter 14 also drives a distributor 14a, which is formed as a binary-to-deeimal converter. Distributor 14a is provided with eleven output lines 32a through 32k. The percentage distortion to be imparted to the generated code trains is determined by the setting of contact 34 with respect to the output lines 32b through 32]'. Lines 32a and 32k can be considered as one. Distortion markers DM are obtained from the selected line in the form of a spike, such as is obtained by differentiation of a leading edge of a pulse and applied to the distortion circuits 10.

Line 32b is designated as 45% distortion and this distortion value decreases in ve percent steps down to zero percent at line 32k which is open. As shown, contact 34 is set at distortion. Initially the counter 14 is at zero. Upon receipt of the iirst pulse from oscillator 12, counter 14 advances and an output spike simultaneously appears on line 32b. Upon receipt of a second pulse, counter 14 again advances and an output spike appears on line 32e. As counter 14 continues its upward count, an output spike progressively appears on the output lines 32. Upon receipt of the sixth input pulse, a spike appears on line 32g and passes through contact 34 to the distortion circuit 10.

When the tenth pulse is received, the spike appears at output line 32k. Counter 14 is at its upper limit, and, therefore, reverses to count downwardly for pulses eleven through twenty. The output spikes now appear on output lines 32 in reverse order beginning with line 32]'. Upon receipt of the fourteenth pulse, the spike again appears at output line 32g and passes to the distortion circuits 10. Upon receipt of the twentieth pulse, the counter returns to zero and the spike appears on open line 32a. The counter now reverses and is ready to begin the next cycle. Thus during each unit pulse, two spikes which form the distortion markers are generated and passed to distortion circuits 10. In FIGURE 2 these distortion markers DM are shown positioned forthe selected 20% distortion and are True signals. As described, these distortion markers occur in time after and 70% of a unit pulse has elapsed. However, with reference to the point of the unit pulses of the generated characters, the distortion markers occur at *:20% points.

FIGURE 3 shows the distortion circuits portion 10 of FIGURE l. The signals CH, 2B, 2E, SI, and DM are applied to the distortion logic block 40. Additionally, the generated character CH is inverted at 42 and this inverted character C H is also applied to the distortion logic 40. In a like manner, the start-inhibit signal SI is inverted at 44 and this inverted signal SI is applied to distortion logic 40. The waveforms for these two signals are also shown in FIGURE 2.

The CH and signals are also respectively applied to AND gates 46 and 48. A second input to each of these AND gates is the 2B signal. The output of AND gate 46 is applied to the set side of flip-flop 50 while the output of AND gate 48 is applied to the clear side of this ip-flop. From the one output of this flip-flop 50 is a delayed character DC is obtained while the inverse of the signal, D C, is obtained from the zero output. Both of these signals are applied to distortion logic 40.

By reference to the circuit of FIGURE 3 and the waveforms of FIGURE 2, the ease with which the signals DC and are generated can be appreciated. Initially, flipop 50 is set and DC is True. is False. The delayed character is here assumed to be in the stop pulse. The generated character CH is at this time False and O H is True. AND gate 46 is therefore inhibited While gate 48 is enabled, that is, in a condition to pass a True input from the 2B signal. At the 50% point of the start pulse of the character CH, the signal goes True and a True signal is passed to the clear side of nip-flop 50 causing this flipflop to change conducting states. D C goes True and DC goes False. The initiation of the start pulse of the delayed character DC has occurred.

At the end of its start pulse CH goes True; however, the 2B signal goes False at this time and because of an absence of coincidence at gate 46, no signal is passed to liip-op 50 and the outputs of this flip-op are unchanged. Half-way through the first information bit of the generated character CH, the signal goes True and the output of AND gate 46 goes True, setting flip-flop 50. The delayed character DC goes True while its inverse signal D C goes False. The start pulse of the delayed character is now complete and by comparison of the delayed character DC withthe generated character CH, it is seen that the start pulse has been delayed one-half unit pulse.

The generated character CH stays True through the end of the second information bit and, accordingly, no change can occur in the conducting states of flip-flop 50. Thus, DC remains True and D C remains False. At the end of the second information bit CH goes False and H goes True; however, also goes False at this point and coincidence does not occur at either gate 46 or 48. The third information bit of the generated character is a spacing condition, and half-way through this 'bit coincidence occurs at AND gate 48 when is found True and 2B goes True. The output of AND gate 48 goes True and clears ip-op 50, reversing its conducting states. DC goes False and DO goes True. Thus, by examination, it is seen that the delayed character DC pulse train continues to trail the generated character CH pulse train by one-half unit pulse. At the end of the third bit CH goes True, however, 2 B- at this time goes False and no coincidence occurs at gate 46. Half-way through the fourth bit it is found that CH is True and that E goes True. Flip-flop 50 is set and its outputs again reverse state. DC goes True and D C goes False.

No further change occurs until half-way through the fifth bit of the generated character CH. At this time both inputs to AND gate 48 are True and flip-flop 50 is cleared. DC goes False and D goes True. The next transition of the delayed character DC occurs half-way through the first stop element of the character CH. At this time both inputs to gate 46 are True and flip-flop 50 is set. DC goes True and D C goes False and the stop condition of the delayed character begins. Because the illustrative generated character has a two-unit stop pulse, the stop condition of the delayed character is also of a two-unit length and, accordingly, the True condition exists in the delayed character until half-way through the start pulse of the next generated character. At this time, the inputs im and 2B at AND gate 48 are both True and flip-flop 50 is cleared.

The delayed character DC goes False and its inverse goes True. The start pulse of the next delayed character has begun.

As can be seen from FIGURE 2 and the above description, the entire delayed character DC follows exactly the waveform of the generated character CH except that it is delayed by a one-half unit pulse period. `Regardless of the code pattern of the generated character CH, this delay relationship holds true for any code train, be it start-stop or synchronous.

In FIGURE 4 there is shown a distortion logic 40 which will function to produce marking bias or spacing bias, as desired. The delayed character, distorted as desired, forms the output signal. According to the definition of marking bias, it occurs as an advanced space-to-mark transition. By observing the four waveforms CH, 'C H, DC and of FIGURE 2, it is seen that during the onehalf unit pulse period preceding the space-to-mark transition of the first information bit of the delayed character DC, only the signals CH and DC are True. As shown in FIGURE 4, AND gate 62 has been provided with the signals CH and T applied to two of the inputs. The third input to the AND gate 62 is for application of the distortion markers DM. The fourth input, labeled SB, is open during generation of marking bias and has no effect on the gate. When the signals CH and D G are both True, gate 62 is enabled for the passage of a distortion marker DM.

Line MB in FIGURE 2 shows a distorted output signal containing marking bias. Assume that initially llip-op 60 (FIG. 4) is set and its output is True. When DO goes True, flip-flop 60 is cleared, and its output undergoes a transition from a True to a False state signifying the initiation of the start pulse in the output signal. As can be seen, the output signal is, so far, following the delayed character. Half-way through the start pulse the just-described one-half pulse period begins where CH and D C are True. As described earlier, with regard to FIGURE 1, the distortion markers have been selected to occur at times corresponding to 20% distortion. With reference to the delayed character, these markers occur at i20% about the zero percent points of the unit pulses. During this one-half unit pulse period, such a distortion marker occurs. See line DM in FIGURE 2. It is a True signal and causes the output of AND gate 62 and OR gate 64 to go momentarily True. For ease of description, the distortion marker DM can be considered to pass through AND gate 62 and OR gate 64. Flip-flop 60 is triggered to its set state and its one output goes True. The space-to-mark transition of the rst information bit of the output signal is advanced by 20%. Therefore, marking bias has been generated.

The output signal stays True until the end of the second information bit. At this time goes True and clears flip-flop 60. The output signal goes False and a spacing condition exists for the third information bit. The fourth information bit is a mark; therefore, beginning half-way through the third information bit, both CH and D G are True. For the ensuing one-half pulse period, AND -gate 62 is enabled for the occurrence of a True distortion marker. Twenty percent before the ideal transition point for the fourth information bit this distortion marker arrives at gate 62. The output of this gate goes True and, accordingly, the output of OR gate 64. lFlipflop 60 is set and the output signal goes True. Twenty percent marking bias has again been created.

The output signal stays True until ITC goes True and clears flip-flop 60 at the end of the fourth information bit. The output signals then stay False until a point in time 20% before the beginning of the stop pulse when another distortion marker DM is generated and passes through AND gate 62 and OR gate 64 to set flip-flop 60. AND gate 62 is again enabled because the signals CH and D C are True for the one-half pulse period preceding the ideal space-to-mark transition of the delayed character stop element. Thus, the stop element of the output signal also contains marking bias. At the end of the stop element, clears Hip-Hop 60 and the output signal goes False, signifying the mark-to-space transition of the start pulse of the next character. A complete character has now been provided with marking bias.

Switch 68 in FIGURE 4 permits the operator to select either marking bias or spacing bias in the output signal. With the switch 68 in the MB position shown, marking bias alone occurs in the output train. AND gate 66 is inhibited because one input is grounded. For spacing bias, the contact is moved to the SB position removing ground from gate 66 and applying this inhibiting potential to gate 62. While a manual switch is shown here, it is obvious that other switching means could be used, such as a flip-flop which would alternate between marking bias and spacing bias on successive characters.

For spacing bias, as shown in line SB of FIGURE 2, the output signal begins in a True state to signify the stop element, and flip-op 60 is set. At the ideal space-tomark transition for the start pulse the signal goes True and clears ip-ilop 60. The output signal goes False. Because spacing bias occurs as a retarded space-to-mark transition, gate 66 is made responsive to distortion markers occurring after the ideal space-to-mark transition point of the delayed character. By examination of FIGURE 2, it is seen that both the undistorted character CH and the delayed character DC are True during the one-half unit pulse period following this transition, and AND gate 66 is connected to receive these two signals.

The first space-to-mark transition in the delayed character DC occurs at the tirst information bit. The output signal SB stays False throughout the start pulse and into this rst information hit until such time as a distortion marker occurs. Assuming that 20% distortion has again been selected, a distortion marker occurs 20% of a unit pulse after the tirst information bit begins. Gate 66 passes this marker, as does OR gate 64, to set flip-flop 60. The one output of ip-tlop 60 goes True and the output signal SB accordingly undergoes a space-tO-mark transition. As seen by waveform SB, 20% spacing bias has been generated.

The output signal SB stays True until goes True at the end of the second information bit and clears flip-flop 60. The output signal SB goes False and stays False throughout the third information bit and into the fourth information bit at which time CH and DC are again True. At the 20% point of this bit a True distortion marker passes through gate 66 and OR gate 64 to set flip-Hop 60. The output signal goes and stays marking throughout the remainder of this fourth bit and then goes spacing for the ifth information bit when D C clears flip-flop 60. The output remains spacing until 20% into the rst stop element. At this time a distortion marker arrives at gate 66 and, nding this gate enabled because both the signals CH and DC are again True, passes through this gate and OR gate 64 to set flip-flop 60. The output signal stays True or marking until the end of the second stop element at which time it goes False in response to D C- clearing flip-flop 60. This signies the mark-to-space transition of the next character start pulse. complete character has been provided with spacing las.

If end distortion is desired, one form of circuit which can be used in the distortion logic 40 is shown in FIG- URE 5. As can be observed, it is similar in appearance to the bias logic of FIGURE 4. A flip-flop 70, from which the distorted output signal is obtained, is controlled primarily by the output of one of tWo AND gates 72 and '74, and a delayed character signal DC. Switch 76 is provided to permit the user to select either marking end distortion or spacing end distortion. With the switch 76 positioned as shown, a ground signal inhibits the operation of AND gate 74 while the gate 72, which determines marking end distortion, is uninhibited. AND gate 78 is utilized in the generation of the start pulse. The output of the three AND gates is applied to OR gate 80.

In operation, flip-flop is in the set condition initially and its one output is True, signifying the stop pulse as shown at the left end of waveform ME of FIGURE 2. The first transition o-f the output signal is the mark-tospace transition at the beginning of the start pulse. Because distortion in a telegraph signal is preferably referenced with respect to the start pulse, it is desirable that this transition be undistorted. Therefore, to ensure that the start pulse transition occurs at the ideal point, AND gate 78 is provided with two inputs, namely, SI and E. The start inhibit signal SII is True only during the start pulse of the generated character CH and is False at all other times. The T signal goes True half-Way through the start pulse of the character CH and, therefore, occurs at the ideal transition point for the delayed character at the ideal transition point for the delayed character. Thus, at this ideal transition point, coincidence occurs at AND gate 78 and its output goes True. The output of OR gate 80 goes True and clears ip-flop 70. The output signal goes False to form the start pulse.

The output signal stays False or spacing until tlip-op 70 is set by the delayed character signal DC going True at the beginning of the first information bit. The output signal ME follows, and stays True or marking for the duration of the rst and second information bits.

Marking end distortion is evidenced by a retarding of the mark-to-space transition. AND gate 72 is, therefore, controlled by the OH and signals because both of these signals are True for the one-half unit pulse periods following ideal mark-to-space transition points. At the end of the second information bit when the delayed character goes False, C H and D O are True and AND gate 72 is conditioned to pass a distortion marker DM. The output signal stays marking until the point in time corresponding to the selected .20% marking end distortion occurs. At that time the generated distortion marker passes through AND gate 72 and OR gate 80 to clear ip-op 70, The output signal goes False and marking end distortion has been generated.

The output signal is True at the end of the third information bit when flip-flop 70 is set by the signal DC. At the ideal mark-to-space transition point for the end of the fourth information bit a one-half unit pulse period begins in which the signals 'O H and are again True. When the distortion marker is generated at the selected 20% point, it passes through the enabled AND gate 70 .to OR gate 80 and onto tlip-tiop 70. This flip-op is cleared and the output signal goes False.

The fth information bit is a spacing pulse and the output signal, therefore, stays False or spacing until the end of this information bit at which time DC goes True to set again flip-flop 70. The output character is now in the stop pulse. At the end of the second stop element, SI is found True and E becomes True. The output of AND gate 78 goes True. The output of OR gate 80 also goes True to clear hip-flop 70. The one output goes False, signifying the beginning of the start pulse of the next character. A complete character has been provided with marking end distortion.

For the generation of spacing end distortion, switch 76 is put in the position labeled SE. Gate 72 is now inhibited by the ground input at the SE lead. Correspondingly, the ground inhibit input at AND gate 74 has been removed. By referring once again to the waveforms of FIGURE 2 and, in particular, the waveform labeled SE, the operation of FIGURE 5 for the generation of spacing end distortion can be better understood. Initially, consider iliptiop 70 in the set state whereby its one output is True signifying the stop element of an output character.

Spacingend distortion is evidenced by an advanced mark-to-space transition. AND gate 74 is, therefore, controlled by the C and DC signals because both of these signals are True for the one-half unit pulse periods preceding mark-to-space transitions. Thus, for the one-half unit pulse period immediately preceding the ideal mark-tospace transition of the start pulse, the signals C H and DC are True. Normally, AND gate 74 would be conditioned to pass any distortion marker generated during this period. However, if such were to occur, Hip-flop 70 would be cleared and the start pulse would be displaced. In order to avoid this distortion of the start pulse, the inverted start inhibit signal S is applied to AND gate 74. S is False at this time and prevents the output of AND gate 74 going True. Thus, the arrival of a distortion marker has no effect on this AND gate. The output signal continues True until the occurrence of the ideal point for the start mark-to-space transition. Because the signal SI is True at this point, as previously explained, then signal 2B', upon going True, causes the output of AND gate 78 and OR gate 80 to go True and clear flip-flop 70. The output of ilip-op 70 goes False and the output character SE is in the start pulse.

The start pulse continues until the beginning of the rst information bit which, as can be seen by the delayed character DC, is here a marking pulse. When the DC signal goes True, flip-flop 70 is set and the output signal goes True. For the duration of the iirst information bit and half-way through the second bit, the SE output waveform stays True. Beginning at the half-way point of the second information 'bit and for the next one-half unit pulse period, both the E and DC inputs to AND gate 74 are True. Since the S-I signal is also True, this AND gate is enabled. Assuming that 20% distortion is again selected at counter 14 in FIGURE l, then at the point in time 20% prior to the ideal transition point at the end of the second information bit, the True distortion marker DM arrives at AND gate 74 and passes therethrough and also through OR gate 80l to clear ip-flop 70. The output goes spacing. The end of a marking pulse has been advanced and, accordingly, spacing end distortion has been generated.

The output signal stays spacing until the signal DC sets ip-op 70 at the end of the third information bit. Halfway through the fourth information bit gate 74 again becomes enabled because of the True conditions existing with the signals m and DC. The distortion marker DM which occurs at the point corresponding to 20% distortion passes through AND gate 74 and OR gate 80 to clear flipop 70. The output signal goes False.

The output signal SE stays spacing for the fifth information bit at the end of which it goes marking or True in response to the True DC signal setting flip-op 70. The character is now in the stop pulse and stays there for the two-unit stop element period at which time it goes spacing to signify the start of the next character. Once again, no displacement of the start transition occurs because of the inhibit applied by the False S signal at AND gate 74. Thus, even though C H and DC are True again for the one-half unit pulse period preceding the start transition, no distortion marker will pass to clear flip-op 70. The start transition is again caused by the True signals SI and 2B applied at AND gate 78. A complete character has been provided with spacing end distortion.

The circuits of FIGURES 4 and 5, therefore, are two embodiments which will function as the distortion logic .40 of FIGURE 3. As taught, any of the four types of distortion can be generated. If desired, either switch 68 or switch 76 can be changed to an automatic switch such as a flip-flop so that successive characters can alternate between marking bias and spacing bias, or marking end distortion and spacing end distortion.

It is often desirable to have for testing or maintenance purposes, a code generator which switches consecutively between the four different types of distortion. In other words, the rst generated character is distorted With marking bias, the next character-spacing bias, the next character-marking end distortion, and the next characterspacing end distortion, and then the cycle repeats. Rather than combining here the logic circuits of FIGURES 4 and 5, together with the necessary switching and supplementary logic, the logic circuit of FIGURE 6 is provided. In contrast with FIGURES 4 and 5, this circuit is designed on the basis of False logic rather than True logic. The waveforms for the signals generated by the circuits of FIGURES 1 and 3 will remain as shown in FIGURE 2; however, by definition, the upper portion of these waveforms will be False while the lowermost portions will be True. Rather than redrawing FIGURE 2, the pertinent waveforms have been relabeled for reference in the right hand column of this figure under the heading FOR FIG. 6.!!

In FIGURE 6, the input AND gates used in the logic of FIGURES 4 and 5 have been replaced by OR gates 100, 102, 104, 106, and 108. The outputs of OR gates and 102 are applied to a NAND gate 110 while the outputs of OR gates 104, 106, and 108 are applied to another NAND gate 12. The output of NAND gate 110 is applied to the clear input of bias flip-flop 114. The set side of this hip-flop is controlled by the DC signal. The output of the zero side of flip-Hop 114 is applied to one input of OR gate 116. The output of this OR gate is applied to one input of NAND gate 118 whose output forms the distorted output signal.

The output of NAND gate 112 is applied to the set side of end-distortion ip-op 120. The clear side is controlled by the signal. The output from the flip-flop 120 is taken from the zero side and applied to one input of OR gate 122. The output of this OR gate is applied to the second input of NAND gate 118.

The second input of each of OR gates 116 and 122 is controlled, respectively, by the zero output and the one output of Hip-flop 124. This Hip-flop acts as a switch to determine whether bias or end distortion will appear in the output. Flip-flop 124 is driven by the zero output of flip-flop 126. The output of this latter flip-flop determines whether marking or spacing distortion will occur.

Flip-flop 126 is driven by the 'S signal applied to its toggle input. As shown by FIGURE 2 and with reference to the False and True designations on the right hand side, it is seen that the signal goes True at the beginning of the start pulse of the generated character CH. Thus, just prior to the start of each output character, switching occurs to provide a new type of distortion. By the arrangement shown in which the two flip-flops are connected in tandem, the four types of distortion will sequentially appear in the output code train.

Assume initially that ilip-llop 124 is in the set state so that the True condition on the one output is being applied to OR gate 122. Under such condition the output of this OR gate stays True. The False condition at the zero output of flip-flop 124 is applied to OR gate 116; therefore, the output of this OR gate will follow whatever condition is established by the input from ip-flop 114. Assume also that iiip-op 126 is clear so that the zero output is True and the one output is False. Accordingly, line 128, which is connected to OR gate 100, is False, while line 130 holds OR gate 102 True. So conditioned, the logic of FIGURE 6 generates a spacing bias in the irst character of the cycle. Note that with the output of OR gate 122 held in the True state until such' time as flip-flop 124 is toggled, any end distortion which might be generated by the logic of the lower portion of FIGURE 6 has no effect on the output of this OR gate. Accordingly, for the discussions of bias distortion there is no need to refer to what occurs in the end distortion logic circuitry.

Line SB of FIGURE 2 shows that the output of FIG- URE 6 is initially False, which corresponds to a marking condition. The start transition of the delayed character signal DC is a True signal which sets ilip-llop 114, previously clear. The zero output of this flip-flop goes False and because there arenow two False inputs at OR gate 116, its output goes from True to False. NAND gate 11S now has a False input from OR gate 116 and a rTrue input from OR gate 122. Its output goes from False to True to indicate the start transition and stays True, or spacing, throughout the start pulse.

Beginning with the ideal transition point for the first information bit, an inspection of the waveforms CH and DC shows that at least for the next one-half unit pulse period both of these signals will be False and OR gate 100 will be enabled. Again selecting the 20% disortion ligure, at the point in time corresponding to 20% distortion a False distortion marker DM arrives at OR gate 100. All inputs are now False and the output of OR gate 100 goes momentarily False. Just prior to this time, both inputs to NAND gate 110 were True. With the arrival of a False signal from OR gate o, the output of NAND gate 110 momentarily goes from a False state to a True state, clearing flip-flop 114. The zero side of this flip-flop goes from a False to a True state and, accordingly, the output of OR gate 116 goes from False to True. Two True conditions now appear at NAND gate 118 and its output goes False or marking. As shown by line SB, this space-to-mark transition has been retarded by twenty percent. Spacing bias has been generated in the output signal.

The signal DC stays False until the end of the second information bit and so does the output signal SB. At the end of the second information bit, DC goes True and sets flip-flop 114. The zero side goes False and with two False inputs now at OR gate 116, its output also goes False. A False and True input now appear at NAND gate 118 and its output goes True. Thus, for the third information bit a spacing condition exists. Beginning at the ideal transition point for the end of the third information bit, the signals CH and DC are both again False. When the exemplary DM occurs, it causes the outputs of OR gate 100 and NAND gate 110 to change momentarily as previously described. Flip-flop 114 clears. The output of OR gate 116 now goes rl`rue in response to the True input from ilip-op 114 and two True signals again appear at the input to NAND gate 118. The output signal goes False. Inspection of line SB shows that 20% spacing bias has also occurred for this space-to-mark transition.

At the end of the fourth information bit DC goes True setting flip-flop 114. Both inputs to OR gate 116 are now False and its output goes False. Because of the appearance of a False condition at one of the inputs to NAND gate 118 its output goes True, causing a spacing pulse in the output train for the fifth bit. Spacing bias also occurs at the first stop element. At the ideal transition point following the end of the fifth information bit, the signals CH and DC are both False. OR gate 100 is again conditioned to pass the distortion marker DM when it occurs` As previously explained and hereafter in this description in order to avoid needless reptition, arrival of a False distortion marker at an enabled input OR gate, will cause the output of that OR gate and the subsequent NAND gate to change condition momentarily and thus clear ip-flop 114 or set Hip-flop 120, as appropriate.

The distortion marker occurs at the 20% distortion point and ip-lop 114 is Cleared. lts True output causes the output of OR gate 116 to change from False to True. Both inputs to NAND gate 118 are now True and its output goes False. The output of NAND gate 11S stays False until the end of the second stop element. At that time the delayed character DC goes True and sets the flip-flop 114. The zero output of this llip-flop goes False and the output of OR gate 116 goes False. With a False input at NAND gate 118, its output goes True signifying the start pulse of the next character. The character shown in line SB is complete.

One-half unit pulse before the end of character SB occurred, the inverted start inhibit signal 'S went True. This change of states caused flip-flop 126 to toggle and its one output went True. Conversely, its zero output went False. Flip-flop 124 was unaffected. With line 128 True and line 130 False, OR gate 100 is inhibited for the next character while OR gate 102 is uninhibited.

Because the signal DC has set flip-op 114, the character shown in line MB of FIGURE 2 is in the start pulse. One-half unit pulse after the start transition occurs, both the signals CH and are False. OR gate 102 is conditioned to pass a distortion marker. As shown by line DM, this distortion marker occurs early by twenty percent with respect to the ideal transition. Its arrival causes flip-flop 114 to be cleared. The zero output of flip-Hop 114 goes from a False to a True state. With an input to OR gate 116 now True, its output goes True and True signals appear at both inputs to NAND gate 118. The output signal goes from a True to a False state indicating a marking condition. Since this transition is advanced, marking bias has occurred.

The output signal stays False until the end of the second information bit at which time it goes True when pilop 114 is set by DC. The zero output of this flip-flop goes False. Both inputs to OR gate 116 are now False and its output goes False and the output signal from NAND gate 118 goes True. The output stays spacing until a distortion marker again causes an early space-to-mark transition twenty percent before the ideal transition point for the fourth information bit. At that time a one-half unit pulse period is in progress in which both the signals CH and DE are again False and OR gate 102 is enabled. Flip-Hop 114 is cleared and the True signal appearing at its output causes the output of OR gate 116 to follow. Both inputs to NAND gate 118 are now True and its output goes False.

At the end of the fourth information bit, the signal DC goes True setting ip-ilop '114 and causing ultimately, as aforedescribed, the output of NAND gate 118 to change from a False to a True state. The fifth information bit is, therefore, a spacing condition. The first stop element is also distorted because one-half unit pulse before the ideal transition point for the beginning of the first stop element, the signal CH and DO are both False. OR gate 102 is enabled for the arrival of the 20% distortion marker, which arrival causes the flip-Hop 114 to clear. The True condition at its zero output passes through OR gate 116 to the input of NAND gate 118. Both inputs to this NAND gate are, therefore, True and its output goes False, signifying the marking condition. The output signal stays marking for the duration of the character, and a cornplete character containing marking bias has been provided. One-half unit pulse before the end of the character MB, SI goes True, toggling nip-flop 126 to the clear state. Line 130 goes True and line 128 goes False. Flip-flop 124 is also toggled by the True signal from the output of flip-flop 126 and it changes state. The zero output goes True and this condition replaces the False input at one input of OR gate 116. The one output from flip-flop 124 goes False, causing a False signal to appear now at one input to OR gate 122. Thus, until flip-flop 124 is again toggled, the True signal at OR gate 116 will hold the output of this OR gate True regardless of the condition of the other input. Bias cannot appear in the output signal and the system is set to provide end distortion.

Flip-flop is found at this time in the clear state because the input signal D went True at the ideal transition point for the rst stop element of the previous character MB The zero output of this ip-op 120, which forms the second input to OR gate 122, is True. The

13 True-toFalse change at the other input of OR gate 122 caused by flip-flop 124 has no effect on the output signal of this OR gate 122 and it remains True at this time. The output of NAND gate 118 stays True or marking.

Line 128, which is False for the forthcoming character, is connected to OR gate 104. This OR gate is used in the determination of spacing end distortion. Marking end distortion will not occur because of the True inhibiting input applied to OR gate 108 on line 130. As discussed previously, it is preferable to avoid end distortion of the start in order to have a stable reference point. During the one-half unit pulse period preceding the arrival of the start transition, the signals ChH and DC are both False and OR gate 104 would normally be responsive to the receipt of a distortion marker. To prevent distortion of the start pulse the inverted start inhibit signal -S-I is also applied to OR gate 104. is True for a one-half unit pulse period before and after the start transition and it prevents the output of this OR gate from going False `during this time period.

To obtain the start transition for the output signal, use is made of OR gate 106. At the end of the stop pulse of the terminating character, the signal SI is in a False state. At the ideal transition point goes False. The output of OR gate 106 goes from a True condition to a False condition. Just prior to this time, all three inputs to NAND gate 112 were True and its output was False. The False condition from OR gate 106 causes the output of NAND gate 112 to go from a False to a True state setting flip-flop 120. The zero side of flip-flop 120 goes from a True to a False state. Both inputs to OR gate 122 are now False and its output goes from True to False, placing a False condition at the lower input of NAND gate 118, The upper input is held True by the output of OR gate 116 and the output of NAND gate 118 goes from False to True. This is the start transition. See line SE of FIGURE 2.

The output stays spacing until the ideal transition point for the beginning of the first information bit. At this time D C goes True, clearing flip-flop 120. Its output goes True, and with a True input now present at OR gate 122, its output goes True also. Two True conditions again exist at the two inputs to NAND gate 1187 causing its output to go False or marking. This output signal stays marking throughout the remainder of the first information bit and into the second information bit. Beginning halfway through this second information bit m and DC are seen to be False. The one-half pulse period in which OR gate 104 is responsive to the arrival of a distortion marker DM is now present. Assuming that the distortion marker is selected, its arrival causes an -output change temporarily at OR gate 104 and NAND gate 112. Flipop 120 is set and its zero output goes False. Two False states now occur at the input to OR gate 122 and its output goes from a True to a False state. With one input to NAND gate 118 now False, the output signal goes from False to True. An advanced mark-to-space transition in the output signal, which corresponds to spacing end distortion, has occurred and is shown in line SE.

The output stays spacing until the end of the third information bit when D C goes True and clears Hip-flop 120. Its zero output goes True and applies a True state at one of the inputs to OR gate 122. The output of this OR gate also goes True. Two True conditions again exist at NAND gate 118 and its output goes False which corresponds to a marking pulse in the output signal. Halfway through this fourth information bit the signals and DC are both again False. This condition will exist for the next one-half unit pulse period. At the time corresponding to twenty `percent distortion, a distortion marker DM arrives at OR gate 104. Flip-flop 120 switches states and its zero output goes False. The output of OR gate 122 goes False and the output of NAND gate 118 goes True. This corresponds to a mark-to-space transition in the output signal and, as can be seen by line SE of FIGURE 2, this transition occured early, corresponding to spacing end distortion.

The fifth information ybit is a space pulse and the output signal stays True or spacing until the ideal transition time of the rst stop element. At this time D G goes True clearing flip-flop and causing ultimately, as aforedescribed, the output of NAND gate 118 to change fro-m a True condition to a False condition. The output character is now in the stop pulse and it stays there for its two-element period. As described previously, half-way before the ideal start transition of the next character the signal E I goes True, holding the output of OR gate 104 True and preventing the passage of a distortion marker and, thereby, the occurrence of spacing end distortion of the stop pulse.

When the signal 'ST goes True, it also toggles flip-flop 126 `causing the one output to go True and the zero output to go False. For the next character, OR gate 104 has a continuous True condition supplied at one of its inputs by line 128 and is inhibited. In contrast, OR gate 108 can be utilized to initiate marking end distortion because line is now False.

At the ideal point for the start transition it is found that the signal SI is False and that E goes False. The output of OR gate 106 goes False and the output of NAND gate 112, accordingly, goes True. Flip-flop 120 is set. The zero side of this flip-flop goes False and with two False inputs to OR gate 122, its output goes False. A False and True condition exists at NAND gate 118 and its output goes True signifying the start transition in the output signal. Because this transition has occurred at the ideal point, there can be no marking end distortion and, accordingly, the output stays spacing until the end of the start pulse. The first information bit is a marking pulse and at the ideal transition point, D O goes True clearing flip-flop 120. The Zero output of this flip-flop goes True, the output of OR gate 122 goes True, and the output signal from NAND gate 118 goes False. This output train stays marking through two full elements.

At the ideal transition point for the beginning of the third information bit, the signals m and D@ are both False in which state they remain for a one-half unit pulse period. Accordingly, OR gate 108 is now enabled. The exemplary twenty percent False distortion marker arrives and because of this coincidence of four False inputs at OR gate 103, the output of this gate goes momentarily False. The output of NAND gate 112 goes momentarily True and flip-flop 120 becomes set. At the zero side of this flip-flop a False condition occurs which causes the output of OR gate 122 to go False. A True input and a False input now exist at NAND gate 118. The output signal goes True. By observing waveform ME of FIG- URE 2, it is seen that a retarded mark-to-space transition has occurred which corresponds to marking end distortion.

At the end of the third information bit 'D goes True clearing flip-flop 120. Its zero side goes True, the output of OR gate 122 goes True, and the output of NAND gate 118 now goes False. This marking condition exists in the output signal -for the fourth bit and extends into the fifth information bit. Beginning at the ideal transition point between the fourth and fifth bits, the signals OH- and D C are both False. The arrival of the twenty percent distortion marker at enabled OR gate 108 results, as previously described, in the setting of flip-flop 120. The output of this flip-flop at the zero side goes False which causes the output of OR gate 122 to go False. The output of NAND gate 118 now goes True because one of its inputs is False. This mark-to-space transition is again retarded, as seen by line ME and, once again, marking end distortion has been provided.

The output remains spacing until the ideal transition point for the stop element. At this time goes True,

clearing the flip-flop 120 and and resulting in the output signal from NAND gate 118 going False or marking. This marking condition exists for the full two-unit stop pulse.

Half-way through the second stop element, the signal goes True and toggles flip-flop 126. The one output of this ip-op and, therefore, line 12S goes False, and the zero output of this ilip-tiop and the line 130 goes True. The False to True change at the zero output also togglesflip-flop 124 causing it to change states. The one output of this flip-flop goes True and the zero output ygoes lFalse. The respective inputs to OR gates 116 and 122 are returned to the condition which exists for the generation of bias. The cycle now repeats.

Because the S signal occurred one-half unit pulse before the ideal transition for the start pulse, the actual transition which ends the character ME of the just-described cycle and begins the character SB in the next cycle is generated by the upper portion of FIGURE 6 because the lower portion now has no effect on the output signal. As explained previously in the description of bias, the signal DC goes True at the ideal transition point and sets flip-flop 114, causing the zero output of this flip-flop to go False. Two False input conditions now appear at OR gate 116 and its output goes False. NAND gate 118 has False and True inputs rather than two True inputs, and the output of this NAND gate, which is the output signal, goes from a False state to a True state to signify the start transition.

In the generation of the various input signals used in FIGURE 6, modification of FIGURES 1 and 3 is desired in order to retain logical uniformity. This modification is shown in FIGURE 7. Initially flip-flop 18 is toggled clear and the 2B signal goes True. The True transitions of the signal are used to advance distributor 22. The output line 24a of the start stage of distributor 22 is True when the start pulse is being generated and the signal is obtained from this line. This signal is inverted at 44 to obtain the SI signal.

The construction of switch bank 26 is the same as in FIGURE 1. Accordingly, the serial output of OR gate 30 is the inverted character signal CH. To obtain CH, m is inverted at 42. AND gates 46 and 48 are fed, respectively, the CH and m signals together with the 2B signal. Initially, flip-flop 50 is clear. Half way through the start pulse of the character signal CH, 2B goes True. Coincidence occurs at AND gate 46 and its output goes True. Flip-flop 50 is set and the one side, where the DC signal is obtained, goes True. This is the start pulse. Half way through the first information bit of the character CH, C H- is True and 2B goes True. The output of AND gate 48 goes True and flip-flop 50 is cleared. DC goes False. This is the start of the first information bit. As can be seen by referring to the waveforms of FIGURE 2, the delayed character DC again follows the character CH by onehall:` a unit pulse. The remainder of the delayed character is generated in a like manner.

While one form of a -telegraph character generator has been described in the present specification, other standard techniques can be used. For example, an electronic switching means `can be substituted for the switches 28 so that the bit patterns change for each successive character. Alternatively, CH can be generated from a message matrix or obtained from an externally applied code train. If other than a unit stop pulse length is desired, a synchronizing signal -to reset the various apparatus can be obtained from the pertinent output line of distributor 14, for example. If synchronous signals are being supplied to the distortion logic, the equivalent to a start inhibit signal SI, if needed, could be obtained elsewhere such as from a standard character timer which recycles at the start of a character.

If an undistorted output signal is desired from distortion logic 40, the zero percent output of distributor 14a could be used. If, however, any practical problems are encountered, the zero percent signal can be delayed slightly, e.g., one percent, or instead an undistorted signal can be obtained from line 31.

While the present invention has been described with reference to preferred embodiments, it will be apparent that various modifications may be made therein within the spirit and 4scope of the invention and it is desired, therefore, that lonly such limitations be placed on the invention as are imposed by the prior art.

What is claimed is:

1. A distortion system for'introducing distortion into a pulse train comprising means for providing an undistorted binary type pulse train, means responsive to said last-named means for providing a binary type pulse train delayed in time with respect to said undistorted train, means for receiving said undistorted and delayed pulse trains to form a period receptive to the introduction of distortion as determined by coincidence of said undistortedand delayed pulse trains, means for introducing distortion initiating signals and applying them to said receivin'g'means, said receiving means passing said distortion initiating signals only during said period when said receiving means is enabled by said coincidence of said undistorted and delayed pulse trains, and output means responsive to said distortion initiating signals passed by said receiving means to provide a distorted output pulse train.

l2. A distortion system as claimed in claim 1 wherein said means for providing a delay pulse train delays said pulse train by one-half of a unit pulse length with respect to the undistorted pulse train, and said period is a oriehalf unit pulse period.

3. A distortion system for introducing distortion into a pulse tram to form a distorted output pulse train comprising means for providing an undistorted binary type pulse train, means responsive to said providing means for providing a binary type pulse train delayed by one-halfof .a unit pulse with respect to said undistorted pulse train, means responsive to the coincidence of said undistorted and delayed pulse trains for establishing one-half unit pulse periods receptive to the introduction of distortion, means for introducing distortion initiating signals and applying them to said establishing means, and means responsive to the output of said establishing means for causing distortion in the output pulse train in response to the application of distortion initiating signals to said establishing means during said one-half unit pulse periods of coincidence of said undistorted and delayed pulse trains whereby said distorted output pulse train is formed.

4. A distortion system as claimed in claim 3 wherein said establishing means are gating means which are enabled during one-half unit pulse periods by coincidence of said undistorted and delayed pulse trains.

5. A distortion system as claimed in claim 3 wherein said gating means are a plurality of gates, each of said gates being enabled during different one-half unit pulse periods, and wherein said distortion system further cornprises additional means for individually selecting only one of said gates to be enabled during one-half unit pulse periods which occur during a predetermined length of said output pulse train.

6. A distortion system as claimed in claim 4 wherein said means for providing an undistorted binary type pulse train provides both said undistorted pulse train and its inverse, and said means for providing a delayed binary type pulse train provides both said delayed pulse train and its inverse, and said gating means are enabled during said one-half unit pulse periods by predetermined coincidence of said undistorted and delayed pulse trains and their inverse.

7. A distortion system as claimed in claim 6 wherein said gating means are a plurality of coincidence gates which are enabled during said different one-half unit pulse 17 periods by predetermined logical states of said undistorted and delayed pulse trains and their inverse.

8. A distortion system for introducing distortion into a pulse train to form a distorted output pulse train comprising means for generating an undistorted binary type pulse train inuluding its inverse signal, means for generating a signal having twice the pulse rate of said undistorted pulse train, means responsive to both of said generating means for providing a binary type pulse train, including its inverse signal, delayed by one-half unit pulse with respect to said undistorted pulse train, a plurality of coincidence gates, connected to be responsive to the outputs of said undistorted pulse train generating means and said providing means, which are individually enabled during predetermined one-half unit pulse periods in accordance with the logical states of selected ones of said undistorted pulse train and said delayed pulse train and their inverse signals, means for generating distortion initiating signals and applying same to said gates, each of said gates when enabled acting to pass said distortion initiating signals, and output means responsive to the passage of said distortion initiating signals for causing early or late transitions in the output pulse train whereby said distorted output pulse train is formed.

9. A distortion system as claimed in claim 8 further comprising additional means for preventing said output means during a predetermined length of said output pulse train from causing an early or late transition in the output pulse train in response to distortion initiating signals except during identical one-half pulse periods whereby only one type of distortion is formed in said output pulse train during said predetermined length.

10. A distortion system as claimed in claim 8 wherein said coincidence gates are AND gates which are individually enabled during predetermined one-half unit pulse periods when selected ones of said undistorted and delayed pulse trains and their inverse signals are logically True.

11. A distortion system as claimed in claim 8 wherein said coincidence gates are OR gates which are individually enabled during predetermined one-half unit pulse periods when selected ones of said undistorted and delayed pulse trains are logically False.

12. A distortion system as claimed in claim 8 wherein said output means comprises bistable means which are switched to one stable state in response to the passage of said distortion initiating signals and switched back to its original state in response to predetermined transitions of said delayed pulse train.

13. A distortion system as claimed in claim 12 wherein said bistable means are a plurality of flip-flops and said output means further comprises output gating means responsive to the output of said ip-flops.

14. A distortion system as claimed in claim 13 further comprising additional means for preventing said output means during a predetermined length of said output pulse train from causing an early or late transition in the output pulse train in response to distortion initiating signals except during identical one-half pulse periods whereby only one type of distortion is formed in said output pulse train during said predetermined length, said additional means including enabling means for selectively enabling one of said output gating means.

15. A distortion system as claimed in claim 14 wherein said additional preventing means including said enabling means are a pair of serially-connected ilip-ops, the output of said flip-Hops being connected to said output gating means and said coincidence gates, and. means for periodically triggering said serially-connected flip-Hops.

16. A distortion system as claimed in claim 8 in which said output pulse train is a telegraph code train and said output means, when causing an early or late transition, advances or retards the transitions in said telegraph code train in accordance with the type of distortion selected References Cited UNITED STATES PATENTS 3,124,705 3/1964 Gray 307-265 X 3,145,342 8/1964 Hill 307-215 X 3,153,733 10/1964 De Bolt et al 307-247 X 3,244,986 4/1966 Rumble 307-293 X 3,270,288 8/ 1966 Hackett 307-268 X JOHN S. HEYMAN, Primary Examiner R. C. WOODBRIDGE, Assistant Examiner U.S. Cl. X.R.

Patent No. 3 :482,117

Dated 2 December 1969 Inventor(s) J. L. Wallace, Jr.

Column 5, Line 8:

Column 6, Line 20: T-' a 3 Column 8, Line 19: delayed character" It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

"is" should be deleted.

"DC", second occurrence, should be "at the ideal transition point :for the should be deleted.

4. Column 9, Line 57: Insert nput between "inhibit" and "applied".

5. Column l0, Line 24: "l2" should be 1l2..

6 Column l0, Line 65: "a" should be deleted.

7. Column ll, Line l6l: "reptition" should be --repetition.

8. Column l3 Line ll Insert -pulse between "start" and H in" 9. Column 14, Line 2: "occured" should be occurred.

l0. Claim 8, Column 17, Line 6: "inuluding" should be including.

SIGNED ND SEALED JUN 16 1970 (SEAL) Aman EdwardlLFlemhmJr.

no m M: l c". m* Aueshng om oamissioner or Patents F ORM IDO-1050 (H3-69) 

